Pass-Transistor Adiabatic Logic Using
Single Power-Clock Supply
Vojin G. Oklobdzija, Dragan Maksimovic
and Fengcheng Lin
Department
of Electrical and Computer Engineering
University of Colorado
Boulder, CO 80309-0425
Phone: (303)492-4863, Fax: (303)492-2758, maksimov@colorado.edu
to appear in the IEEE Transactions on Circuits and Systems,
Part II, 1997.
ABSTRACT
We present a new pass-transistor adiabatic logic (PAL) that operates
from a single power-clock supply and outperforms the previously reported
adiabatic logic techniques in terms of its energy use. PAL is a dual-rail
logic with relatively low gate complexity: a PAL gate consists of true
and complementary NMOS functional blocks, and a pair of cross-coupled PMOS
devices. In simulation tests using a standard 1.2u CMOS technology, the
circuit has been found to operate up to 160MHz clock frequency and down
to 1.5V peak-to-peak sinusoidal power-clock supply. Operation of a 1600-stage
PAL shift register fabricated in the 1.2u CMOS technology has been experimentally
verified.