Most projects which require the use of programmable logic make use of the Xilinx Spartan XCS10 FPGA. We use an 84 pin PLCC package, along with PLCC sockets and wirewrap adapters. For programming, we use 18v256 or 18v512 serial EEPROMs. Both the FPGA and the EEPROM can be programmed via JTAG.

For wiring and hardware specifics, refer to the Xilinx technical documentation, available in the lab or online. Chapters on the Spartan and on the 18vX chips both have good schematics for connection. In short, the EEPROM and FPGA should be connected in a JTAG chain, and there should also be a DO/DI connection between the two chips. The Xilinx Data Book 2000 contains several useful sections that you should review before continuing. Chapter 4, starting on page 4-61, describes the Spartan FPGA that we are using. Chapter 5 describes the use of FPGA's with a configuration PROM. Figure 5 on page 5-9 shows the wiring connections for multiple PROM's and FPGA's, which you can adapt for your needs.

Most students become hung-up on the software/programming side of using the FPGA. In the Capstone labs, we use an older version of Xilinx software, in order to support the older parts we use. To use this software simply double-click the "Project Manager" icon on the desktop, or go to Start/Programs/Xilinx Foundation Series 3.1i/Project Manager. NOTE: If weird fatal errors occur, you may need "Power User" privileges on the computer you are using. Contact a TA.

When the program starts, choose "Create a New Project", and select a project name and directory location. Please store your project on the Z: drive or in your group directory, as the computer harddrives may be re-imaged without warning. Make chip and package selections as appropriate for your chip. (Choose type F3.1i, Schematic or HDL, Spartan, S10PC84, and 3 or 4).

To enter a schematic, click on the "and" symbol in the center of the screen. A new schematic page will automatically open. Right-click and select "symbol placement mode" to insert components in your design. The easiest way to connect a signal to an I/O pin it to use a IPAD or OPAD block to a design. Right click a placed IPAD or OPAD and click properties. Add a new parameter called LOC and set its value to Px, where x is the pin number you wish to connect the signal to. When finished, save the design and close the schematic editor.

One of the biggest hang-up encountered by students with the XCS10 involves boundary scan. In order to program the FPGA/EEPROM, the chain needs to respond to JTAG commands. This will not happen when the FPGA is already programmed unless your design includes the BSCAN block. You should always insert the BSCAN block into your design, and connect it to the TDI, TDO, TMS, and TCK schematic blocks.

The implementation stage should now be non-shaded. Click the implementation button, and a window will appear. Say yes to any requests to update the netlist. When you get to the "Implement Design" window, click the options box. Leave the "implementation" selection at Default. Select "Foundation EDIF" or "Off" for the Simulation selection, and choose JTAG for configuration. Select "Edit Options" for the Configuration/Jtag line. Under the "startup" tab, set "Done" to C1, "enable outputs" to C3, and "Release Set/Reset" to C4. Click OK and you return to the "Options" menu. Click OK again, and you return to the "Implement Design" window. Click run. If any errors occur, you will be able to view them via the "Reports" tab in the project manager window.

Ideally, you now have a bit-file somewhere containing your design. The programming button should also be un-shaded now. Click the programming button, and select "PROM File Formatter". DO NOT SELECT "JTAG Programmer"! The Xilinx PROM File Formatter window will open. It usually opens behind the Project Manager window, so bring it to the foreground. Ideally your project bit file should already be added to a data stream titled "Data Stream #1". If not, navigate to your project directory, and manually add the bit file (drag and drop from the right panel). From the File Menu, choose PROM Properties. Set the PROM file format to "EXORmacs", the type to "Serial" the PROM File to "Single Prom" and the PROM Device to XC18V256 (or XC18V512 if appropriate). Choose "Save As Defaults" for your convenience. Then click OK. Click File and "Create Prom As" to save the EEPROM files. Note that while this appears to save a file of the type pdr, it also creates the exo file that we will use in the last step.

Before you program your device, you will need to connect to it via the parallel JTAG cables available from the instructors. Your devices should all be connected via a JTAG daisy chain. We recommend bring the TDI/TDO/TMS/TCK pints to a header. Make sure the VCC pin of the JTAG programming cable is connected to the +5 on your board. At this point, power up your board and ensure that the cables are properly connected.

To actually program your chain of devices, exit the Project Manager, and on the desktop open the "Device Programming" tool. This is also available via Start/Programs/Xilinx WebPACK 4.2/Device Programming. At the opening menu, choose "Configure Devices" and click Next. Select "Boundary Scan Mode" and click next. Choose "Automatically connect to cable and indentify boundary-scan chain". When you click finish, the tool will automatically detect the elements on your chain. Most likely this will be an EEPROM and an FPGA. If the programmer asks you to make any selections about the devices, choose the appropriate part. If the programmer does not detect your devices, re-check your connections. There may also be a problem with your hardware. Right click on a device in the chain and choose "Assign New Configuration File". You must assign your exo file to the EEPROM, and you may optionally assign your bit file to the fpga. To program a device, right-click on it, and choose program. Set any programming options you wish, and click OK. If successful, you will get a big blue notification. Once your EEPROM is programmed, your FPGA should configure itself at power-on with the data stored in the EEPROM. You may power cycle your board and check functionality of the FPGA (assuming you built in some test mechanism).